The IEEE standard, “IEEE 1394-2000 Standard For A High Performance Serial Bus,” Draft ratified in 2000, is an international standard for implementing an inexpensive high-speed serial bus architecture which supports both asynchronous and isochronous format data transfers. Isochronous data transfers are real-time transfers which take place such that the time intervals between significant instances have the same duration at both the transmitting and receiving applications. Each packet of data transferred isochronously is transferred in its own time period. The IEEE 1394-2000 standard bus architecture provides up to sixty-four (64) channels for isochronous data transfer between applications. A six bit channel number is broadcast with the data to ensure reception by the appropriate application. This allows multiple applications to simultaneously transmit isochronous data across the bus structure. Asynchronous transfers are traditional data transfer operations which take place as soon as possible and transfer an amount of data from a source to a destination.
The IEEE 1394-2000 standard provides a high-speed serial bus for interconnecting digital devices thereby providing a universal I/O connection. The IEEE 1394-2000 standard defines a digital interface for the applications thereby eliminating the need for an application to convert digital data to analog data before it is transmitted across the bus. Correspondingly, a receiving application will receive digital data from the bus, not analog data, and will therefore not be required to convert analog data to digital data. The cable required by the IEEE 1394-2000 standard is very thin in size compared to other bulkier cables used to connect such devices. Devices can be added and removed from an IEEE 1394-2000 bus while the bus is active. If a device is so added or removed the bus will then automatically reconfigure itself for transmitting data between the then existing nodes. A node is considered a logical entity with a unique identification number on the bus structure. Each node provides an identification ROM, a standardized set of control registers and its own address space.
The IEEE 1394-2000 standard defines a protocol as illustrated in FIG. 1. This protocol includes a serial bus management block 10 coupled to a transaction layer 12, a link layer 14 and a physical layer 16. The physical layer 16 provides the electrical and mechanical connection between a device or application and the IEEE 1394-2000 cable. The physical layer 16 also provides arbitration to ensure that all devices coupled to the IEEE 1394-2000 bus have access to the bus as well as actual data transmission and reception. The link layer 14 provides data packet delivery service for both asynchronous and isochronous data packet transport. This supports both asynchronous data transport, using an acknowledgement protocol, and isochronous data transport, providing real-time guaranteed bandwidth protocol for just-in-time data delivery. The transaction layer 12 supports the commands necessary to complete asynchronous data transfers, including read, write and lock. The serial bus management block 10 contains an isochronous resource manager for managing isochronous data transfers. The serial bus management block 10 also provides overall configuration control of the serial bus in the form of optimizing arbitration timing, guarantee of adequate electrical power for all devices on the bus, assignment of the cycle master, assignment of isochronous channel and bandwidth resources and basic notification of errors.
As discussed above, an IEEE 1394-2000 device includes the capability to transmit and receive data. This data can be of many different formats. Often data received by an IEEE 1394-2000 device must be processed. This processing includes any or all of displaying, manipulating, forwarding and storing. This processing can be performed in software controlled by the receiving application or in hardware. An example of an isochronous data pipe apparatus for processing received isochronous data, is taught within U.S. patent application Ser. No. 08/612,322, filed on Mar. 7, 1996 and entitled “ISOCHRONOUS DATA PIPE FOR MANAGING AND MANIPULATING A HIGH-SPEED STREAM OF ISOCHRONOUS DATA FLOWING BETWEEN AN APPLICATION AND A BUS STRUCTURE,” which is hereby incorporated by reference.
First-in first-out (FIFO) buffers or memories are typically used as intermediate buffers during a data transfer where a buffer is needed and the order of the data, as received, must be maintained. FEFO's are generally implemented within a random access memory structure. A write pointer is used to keep track of the available memory locations. A read pointer is used to keep track of the occupied memory locations. As data is written to and read from the FIFO buffer, the write and read pointers are incremented, respectively, in order to maintain the order of the data so that the data is output from the FIFO buffer in the same order that it was received. Typically, a FIFO only includes the ability to buffer the data by receiving the data, storing the data, and then providing the data at an output in the same order that the data was received.